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Processing Instruction
Results: 1077

#	Item
741	C OV ER F E AT U RE ARCHITECTURES FOR EXTREMESCALE COMPUTING Josep Torrellas, University of Illinois at Urbana-Champaign Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2009-11-26 21:44:08 Parallel computing Microprocessors Central processing unit Instruction set architectures Multi-core processor Intel MIC CPU cache Application checkpointing Blue Gene Computing Computer architecture Computer hardware
742	Microsoft PowerPoint - pres_extreme09 Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-23 16:59:52 Microprocessors Josep Torrellas Exascale computing Intel Tera-Scale Orders of magnitude FLOPS Central processing unit Instruction set Teraflops Research Chip Computing Computer hardware Electronic engineering
743	AMD’s Mustang versus Intel’s Willamette (A performance analysis for high tech investors) AMD’s near term future looks rosy with Spitfire and Thunderbird getting ready to take on Celeron II and Coppermine with highe Add to Reading List Source URL: www.chip-architect.com Language: English - Date: 2009-05-14 06:18:04 Instruction set architectures Central processing unit CPU cache Cache Computer memory P6 Itanium Alpha 21264 AMD 10h Computer architecture Computer hardware Computing
744	This article appeared in a journal published by Elsevier. The attached copy is furnished to the author for internal non-commercial research and education use, including for instruction at the authors institution and shar Add to Reading List Source URL: www.princeton.edu Language: English - Date: 2012-07-03 10:51:10 World Wide Web Social information processing Community building Cultural economics Graph theory Social network analysis Social networking service Centrality Facebook Networks Software Structure
745	Appears in the 19th IEEE International Symposium on High Performance Computer Architecture (HPCA[removed]Power Struggles: Revisiting the RISC vs. CISC Debate on Contemporary ARM and x86 Architectures Add to Reading List Source URL: research.cs.wisc.edu Language: English - Date: 2013-02-12 23:17:48 Instruction set architectures Central processing unit Reduced instruction set computing X86 Instruction set DEC Alpha Intel Atom Microarchitecture VAX Computer architecture Computer hardware Computing
746	Software Pipelining for (i=1, i<100, i++) { An alternative method of reorganizing loops Add to Reading List Source URL: homepage.cs.uiowa.edu Language: English - Date: 2006-03-28 11:52:24 Central processing unit Classes of computers Register renaming Software pipelining CPU cache Branch predictor Microarchitecture Reduced instruction set computing Pentium Pro Computer architecture Computer hardware Computer engineering
747	Microsoft Word - cscc.doc Add to Reading List Source URL: www.wseas.us Language: English - Date: 2006-09-30 05:26:05 Central processing unit Classes of computers Compiler optimizations Instruction set architectures Microcode Delay slot Microarchitecture Strength reduction DLX Computer architecture Computing Computer engineering
748	A Novel ASIC Design Approach Based on a New Machine Paradigm R. W. Hartenstein, A. G. Hirschbiel, M. Riedmüller, K. Schmidt, M. Weber Universitaet Kaiserslautern, F.B. Informatik, Bau 12, Postfach 3049, D[removed]Kaisers Add to Reading List Source URL: xputer.de Language: English - Date: 2013-11-13 03:37:58 Central processing unit Classes of computers Firmware Microcode Computer Programming paradigm Parallel computing Instruction set Von Neumann architecture Computing Computer architecture Electronics
749	R.W. Hartenstein, A.G. Hirschbiel, M. Riedmuller, K. Schmidt, M.Weber: A High Performance Machine Paradigm Based on Auto-Sequencing Data Memory; HICSS-24, Hawaii Int. Conference on System Sciences, Koloa Hawaii, 1991 A Add to Reading List Source URL: hartenstein.de Language: English - Date: 2012-03-09 12:37:00 Computer hardware Parallel computing Cache Systolic array Instruction set Microcode Computer Computer architecture Central processing unit Computing
750	R. Hartenstein,A. Hirschbiel,K. Schmidt,M. Weber: A Novel Paradigm of Parallel Computation and its Use to Implement Simple High-Performance-HW; Future Generation Computer Systems[removed], p[removed], North Holland A Nove Add to Reading List Source URL: xputer.de Language: English - Date: 2012-03-17 07:12:18 Instruction set Computer Computer engineering Computing Models of computation Electronics Computer architecture Central processing unit Parallel computing Cache

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